PHASE - I

Inverter Schematic

PHASE - I

Inverter Layout

PHASE - I

NAND Schematic

PHASE - I

NAND Layout

PHASE - I

2x1 Multiplexer Schematic

PHASE - I

2x1 Multiplexer Layout

PHASE - II

Transmission Gate Schematic

PHASE - II

Transmission Gate Layout

PHASE - II

TriState Buffer Schematic

PHASE - II

TriState Buffer Layout

PHASE - II

D-FlipFlop Schematic

PHASE - II

D-FlipFlop Layout (TOP)

PHASE - II

D-FlipFlop Layout (BOTTOM)

PHASE - III

1-Bit Register Schematic

PHASE - III

1-Bit Register Layout

PHASE - III

4x16-Bit Decoder Schematic

PHASE - III

4x16-Bit Decoder Layout

PHASE - III

16x16-Bit Register Schematic

PHASE - III

16x16-Bit Register Layout