-------------------------------------------------------------------------------
--
-- Title : Alert Analyzer
-- Design : lab12s07
-- Author : Muhammad S Aman
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : alert_analyzer.vhd
-- Generated : Wed Apr 25 17:36:53 2007
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description : This program when implemented on chip check one's ability to operate a machine or vehicle or even
-- flying a plan. The user have to pass the test which is very easy for someone who is not drunk or tired. Operation
-- of the system is also very easy. The user sees 3 numbers for 0.5 secs individually. After that all the numbers
-- disappear and then the user has to input the required digit with a dial. Turning the dial clockwise will input
-- the numbers and then turning it anti-clockwise will input that number and check it against the required number.
-- After entering all three digits right, the user can operate the machine, otherwise the test starts again.
--
---------------------------------------------------------------------------------------------------
--
--

library ieee;
use ieee.std_logic_1164.all;

entity ose_decoder_fsm is
port(
a : in std_logic; -- from OSE channel A
b : in std_logic; -- from OSE channel B
clk : in std_logic;
rst_bar : in std_logic; -- synchronous reset
cten_bar : out std_logic; -- counter enable control
up_bar : out std_logic; -- counter direction control
dir_chngd : out std_logic -- OSE direction changed status
);
end ose_decoder_fsm;

architecture fsm of ose_decoder_fsm is
type state is (cw0, cw1, cwpe, cwcnt, ccw0, ccw1, ccwpe, ccwcnt);
signal ps, ns : state;
begin
state_reg : process (clk, rst_bar)
begin
if rising_edge(clk) then
if rst_bar = '0' then
ps <=cw0;
else ps <=ns;
end if;
end if;
end process;

next_state : process (ps, a, b)
begin
case ps is
when cw0 =>
if a = '0' then ns <= cw1;
else ns <= cw0;
end if;

when cw1 =>
if a = '1' then ns <= cwpe;
else ns <= cw1;
end if;

when cwpe =>
if b = '0' then ns <= cwcnt;
else ns <= ccwcnt;
end if;

when cwcnt =>
ns <= cw0;

-- counterclockwise rotation

when ccw0 =>
if a = '0' then ns <= ccw1;
else ns <= ccw0;
end if;

when ccw1 =>
if a = '1' then ns <= ccwpe;
else ns <= ccw1;
end if;

when ccwpe =>
if b = '1' then ns <= ccwcnt;
else ns <= cwcnt;
end if;

when ccwcnt =>
ns <= ccw0;

end case;
end process;

outputs : process (ps, a, b) -- output process
begin
cten_bar <= '1'; -- default output values
up_bar <= '-';
dir_chngd <= '0';

case ps is

when cwpe =>
if b = '1' then
dir_chngd <= '1';
end if;

when cwcnt =>
cten_bar <= '0';
up_bar <= '0';

when ccwpe =>
if b = '0' then
dir_chngd <= '1';
end if;

when ccwcnt =>
cten_bar <= '0';
up_bar <= '1';

when cw0 | cw1 | ccw0 | ccw1 =>
null;

end case;
end process;
end fsm;

----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_cntr is
port(
clk : in std_logic; -- clock
clear_bar : in std_logic; -- synchronous clear counter
up_bar : in std_logic; -- count direction control
cten1_bar : in std_logic; -- count enable 1
cten2_bar : in std_logic; -- count enable 2
max_min_bar : out std_logic; -- 0 for maximum/minimum count
qdcba : out std_logic_vector(3 downto 0) -- counter output
);
end bcd_cntr;

architecture behavioural of bcd_cntr is
signal count_int : integer range 0 to 9;
begin
process (clk, clear_bar, up_bar)
begin
if clear_bar = '0' then
count_int <= 0;
max_min_bar <= '1';
elsif rising_edge(clk) then
if ((clear_bar = '1') and (up_bar = '0') and (cten1_bar = '0') and (cten2_bar = '0')) then
if count_int = 8 then
max_min_bar <= '0';
count_int <= count_int + 1;
elsif count_int = 9 then
max_min_bar <= '1';
count_int <= 0;
else
max_min_bar <= '1';
count_int <= count_int + 1;
end if;
elsif ((clear_bar = '1') and (up_bar = '1') and (cten1_bar = '0') and (cten2_bar = '0')) then
if count_int = 0 then
max_min_bar <= '0';
count_int <= 9;
else
max_min_bar <= '1';
count_int <= count_int - 1;
end if;
end if;
end if;
end process;

qdcba <= std_logic_vector(to_unsigned(count_int, 4));

end behavioural;

------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity bcd_7seg is
port (bi_bar : in std_logic;-- blanking input
lt_bar : in std_logic;-- lamp test input
dcba : in std_logic_vector (3 downto 0);--BCD input
seg: out std_logic_vector(6 downto 0) -- segments from a to g
);
end bcd_7seg;

architecture behaviour of bcd_7seg is
signal tmp : std_logic_vector (5 downto 0);
begin
process (lt_bar, bi_bar, dcba(3), dcba(2), dcba(1), dcba(0))
begin
tmp <= (lt_bar, bi_bar, dcba(3), dcba(2), dcba(1), dcba(0));
if ((lt_bar = '0') and (bi_bar = '0')) then
seg <= "1111111";
elsif ((lt_bar = '0') and (bi_bar = '1')) then
seg <= "0000000";
elsif ((lt_bar = '1') and (bi_bar = '0')) then
seg <= "1111111";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0000")) then
seg <= "0000001";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0001")) then
seg <= "1001111";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0010")) then
seg <= "0010010";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0011")) then
seg <= "0000110";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0100")) then
seg <= "1001100";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0101")) then
seg <= "0100100";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0110")) then
seg <= "1100000";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "0111")) then
seg <= "0001111";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "1000")) then
seg <= "0000000";
elsif ((lt_bar = '1') and (bi_bar = '1') and (dcba = "1001")) then
seg <= "0001100";
else seg <= "-------";
end if;
end process;
end behaviour;

------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity mux_4_3x1 is
port(bcd2 : in std_logic_vector(3 downto 0);
bcd1 : in std_logic_vector(3 downto 0);
bcd0 : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
bcd_out : out std_logic_vector(3 downto 0)
);
end mux_4_3x1;

architecture conditional of mux_4_3x1 is
begin
bcd_out <=
bcd0 when sel = "00" else
bcd1 when sel = "01" else
bcd2 when sel = "10" else
"----";
end conditional;

----------------------------------------------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity mux_4_4x1 is
port(bcd3 : in std_logic_vector(3 downto 0);
bcd2 : in std_logic_vector(3 downto 0);
bcd1 : in std_logic_vector(3 downto 0);
bcd0 : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
bcd_out : out std_logic_vector(3 downto 0)
);
end mux_4_4x1;

architecture conditional of mux_4_4x1 is
begin
bcd_out <=
bcd0 when sel = "00" else
bcd1 when sel = "01" else
bcd2 when sel = "10" else
bcd3 when sel = "11";
end conditional;

-----------------------------------------------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg_4bit is
port(clk : in std_logic;
en_bar : in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0)
);
end reg_4bit;

architecture behavioural of reg_4bit is
begin
process (clk)
variable q_v : std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
if en_bar = '0' then
q <= d;
end if;
end if;
end process;
end behavioural;

----------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity comparator_4bit is
port(p, q : in std_logic_vector(3 downto 0);
equal : out std_logic
);
end comparator_4bit;

architecture dataflow of comparator_4bit is
begin
equal <= '1' when p = q else
'0';
end dataflow;

---------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity control_fsm is
port(
clk, rst_bar, start_bar, ose_cten_bar, ose_dir_chngd, ose_up_bar, delay_timed_out, b, com_equal : in std_logic;
no_of_bcds_eq : in std_logic_vector(1 downto 0);
dig0_cten_bar, dig12_cten_bar, dig0_clear_bar, ld_BCD0_bar, gd_cntr, en_gd_cntr_bar, fire : out std_logic;
passed_bar, failed_bar : out std_logic;
sel_BCD_dsply, sel_BCD_cmpr : out std_logic_vector(1 downto 0);
digit_drive_bar : out std_logic_vector(2 downto 0)
);
end control_fsm;

architecture behavioral of control_fsm is
type state is (reset, IDLE, stp_cntr, save_dig0, dig2_delay, dig2_display, dig1_delay, dig1_display, dig0_delay,
dig0_display, clr_dig0, dig2_clear, dig2_chng, dig2_chk, dig1_clear, dig1_chng, dig1_chk, dig0_clear,
dig0_chng, dig0_chk, result);

signal ps, ns : state;

begin

state_reg: process (clk)
begin
if rising_edge(clk) then
if rst_bar = '0' then
ps <= reset;
else
ps <= ns;
end if;
end if;
end process;

nex_state: process ( ps, rst_bar, start_bar, ose_dir_chngd, b, delay_timed_out)
begin
case ps is
when reset =>
if rst_bar = '1' then
ns <= IDLE;
else
ns <= reset;
end if;

when IDLE =>
if start_bar = '0' then
ns <= stp_cntr;
else
ns <= IDLE;
end if;

when stp_cntr =>
ns <= save_dig0;

when save_dig0 =>
ns <= dig2_delay;

when dig2_delay =>
ns <= dig2_display;

when dig2_display =>
if delay_timed_out = '1' then
ns <= dig1_delay;
else
ns <= dig2_display;
end if;

when dig1_delay =>
ns <= dig1_display;

when dig1_display =>
if delay_timed_out = '1' then
ns <= dig0_delay;
else
ns <= dig1_display;
end if;

when dig0_delay =>
ns <= dig0_display;

when dig0_display =>
if delay_timed_out = '1' then
ns <= clr_dig0;
else
ns <= dig0_display;
end if;

when clr_dig0 =>
ns <= dig2_clear;

when dig2_clear =>
ns <= dig2_chng;

when dig2_chng =>
if ose_dir_chngd = '1' and b = '1' then
ns <= dig2_chk;
else
ns <= dig2_chng;
end if;

when dig2_chk =>
ns <= dig1_clear;

when dig1_clear =>
ns <= dig1_chng;

when dig1_chng =>
if ose_dir_chngd = '1' and b = '1' then
ns <= dig1_chk;
else
ns <= dig1_chng;
end if;

when dig1_chk =>
ns <= dig0_clear;

when dig0_clear =>
ns <= dig0_chng;

when dig0_chng =>
if ose_dir_chngd = '1' and b = '1' then
ns <= dig0_chk;
else
ns <= dig0_chng;
end if;

when dig0_chk =>
ns <= result;

when result =>
if delay_timed_out = '1' then
ns <= IDLE;
else
ns <= result;
end if;
end case ;
end process;

outputs: process (ps, ose_cten_bar, ose_up_bar, no_of_bcds_eq, com_equal)
begin
dig0_clear_bar <= '1';
dig0_cten_bar <= '1';
dig12_cten_bar <= '1';
ld_BCD0_bar <= '1';
sel_BCD_dsply <= "00";
sel_BCD_cmpr <= "00";
passed_bar <= '1';
failed_bar <= '1';
fire <= '0';
en_gd_cntr_bar <= '1';
gd_cntr <= '0';
digit_drive_bar <= "111";

case ps is

when reset =>
dig0_clear_bar <= '0';

when IDLE =>
dig0_cten_bar <= '0';
dig12_cten_bar <= '0';

when stp_cntr =>
dig0_cten_bar <= '1';
dig12_cten_bar <= '1';

when save_dig0 =>
ld_BCD0_bar <= '0';

when dig2_delay =>
fire <= '1';

when dig2_display =>
sel_BCD_dsply <= "10";
digit_drive_bar <= "011";

when dig1_delay =>
fire <= '1';

when dig1_display =>
sel_BCD_dsply <= "01";
digit_drive_bar <= "101";

when dig0_delay =>
fire <= '1';

when dig0_display =>
sel_BCD_dsply <= "00";
digit_drive_bar <= "110";

when clr_dig0 =>
gd_cntr <= '1';

when dig2_clear =>
dig0_clear_bar <= '0';

when dig2_chng =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "10";
dig0_cten_bar <= ose_up_bar or ose_cten_bar;
digit_drive_bar <= "011";

when dig2_chk =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "10";
digit_drive_bar <= "011";
en_gd_cntr_bar <= not com_equal;

when dig1_clear =>
dig0_clear_bar <= '0';

when dig1_chng =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "01";
dig0_cten_bar <= ose_up_bar or ose_cten_bar;
digit_drive_bar <= "101";

when dig1_chk =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "01";
digit_drive_bar <= "101";
en_gd_cntr_bar <= not com_equal;

when dig0_clear =>
dig0_clear_bar <= '0';

when dig0_chng =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "00";
dig0_cten_bar <= ose_up_bar or ose_cten_bar;
digit_drive_bar <= "110";

when dig0_chk =>
sel_BCD_dsply <= "11";
sel_BCD_cmpr <= "00";
digit_drive_bar <= "110";
en_gd_cntr_bar <= not com_equal;
fire <= '1';

when result =>
if no_of_bcds_eq = "11" then
passed_bar <= '0';
else
failed_bar <= '0';
end if;
end case;
end process;
end behavioral;

-----------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity result is
port(
clk : in std_logic;
gd_cntr : in std_logic;
en_gd_cntr_bar : in std_logic;
no_of_bcds_eq : out std_logic_vector(1 downto 0)
);
end result;

architecture behavioral of result is
signal bcds_eq : unsigned (1 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
if gd_cntr = '1' then
bcds_eq <= "00";
elsif
en_gd_cntr_bar <= '0' then
bcds_eq <= bcds_eq + 1;
end if;
end if;
end process;
no_of_bcds_eq <= std_logic_vector(bcds_eq);
end behavioral;

--------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity delay is
port(
fire : in std_logic; -- trigger the delay
clk : in std_logic; -- system clock
rst_bar : in std_logic; -- synchronous reset
delayed_out : out std_logic -- delayed output
);
end delay;

architecture behavioral of delay is
constant clock_cycles : integer := 6; -- delay as number of clock cycles
signal count : integer range 0 to 2**20 - 1;
begin
count_down: process (clk)
begin
if rising_edge(clk) then
if rst_bar = '0' then
count <= 0;
elsif count > 0 then
count <= count - 1;
elsif fire = '1' then
count <= clock_cycles;
end if;
end if;
end process;

delayed_out <= '1' when count = 1 else '0';

end behavioral;

---------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity dig0ordig1 is
port(
dig0_m_m_bar, dig1_m_m_bar : in std_logic;
or_max_min : out std_logic
);
end dig0ordig1;

architecture behavioral of dig0ordig1 is
begin
or_max_min <= dig0_m_m_bar or dig1_m_m_bar;
end behavioral;

--------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity alert_analyzer_2 is
port(
a : in std_logic; -- channel a from OSE
b : in std_logic; -- channel b from OSE
clk : in std_logic; -- system clock
rst_bar : in std_logic; -- power on reset
start_bar : in std_logic; -- start input
segments : out std_logic_vector(6 downto 0); -- segments to LED display
digit_drive_bar : out std_logic_vector(2 downto 0); -- to digit drivers
passed_bar : out std_logic; -- passed LED drive
failed_bar : out std_logic -- failed LED drive
);

end alert_analyzer_2;

architecture top_level of alert_analyzer_2 is
signal ose_cten_bar, ose_dir_chngd, en_dig0_bar, ose_up_bar : std_logic;
signal dig0_clear_bar : std_logic;
signal dig0_max_min_bar : std_logic;
signal dig0_qdcba : std_logic_vector(3 downto 0);
signal dig1_max_min_bar : std_logic;
signal dig1_qdcba : std_logic_vector(3 downto 0);
signal dig2_qdcba : std_logic_vector(3 downto 0);
signal max_min01_bar : std_logic;
signal mux4x1_bcd_out : std_logic_vector(3 downto 0);
signal mux3x1_bcd_out : std_logic_vector (3 downto 0);
signal dig0_reg_q : std_logic_vector(3 downto 0);
signal fire, timed_out : std_logic ;
signal equal, ld_BCD0_bar, free_run_bar : std_logic;
signal sel_BCD_dsply, sel_BCD_cmpr : std_logic_vector(1 downto 0);
signal gd_cntr, en_gd_cntr_bar : std_logic;
signal no_of_bcds_eq : std_logic_vector(1 downto 0);

begin

u1: entity ose_decoder_fsm port map (a => a, b => b, clk => clk, rst_bar => rst_bar, cten_bar => ose_cten_bar,
dir_chngd => ose_dir_chngd, up_bar => ose_up_bar);

u2: entity bcd_cntr port map (clear_bar => dig0_clear_bar, clk => clk, cten1_bar => en_dig0_bar,
cten2_bar => en_dig0_bar, up_bar => '0', max_min_bar => dig0_max_min_bar, qdcba => dig0_qdcba);

u3: entity bcd_cntr port map (clear_bar => rst_bar, clk => clk, cten1_bar => dig0_max_min_bar,
cten2_bar => free_run_bar, up_bar => '0',max_min_bar => dig1_max_min_bar, qdcba => dig1_qdcba);

u3b : entity dig0ordig1 port map (dig0_m_m_bar => dig0_max_min_bar, dig1_m_m_bar => dig1_max_min_bar,
or_max_min => max_min01_bar);

u4: entity bcd_cntr port map (clear_bar => rst_bar, clk => clk, cten1_bar => max_min01_bar,
cten2_bar => free_run_bar, up_bar => '0', max_min_bar => open, qdcba => dig2_qdcba);

u5: entity bcd_7seg port map (bi_bar => '1', dcba => mux4x1_bcd_out, lt_bar => '1', seg => segments);

u6: entity mux_4_4x1 port map (bcd0 => dig0_reg_q, bcd1 => dig1_qdcba, bcd2 => dig2_qdcba, bcd3 => dig0_qdcba,
sel => sel_BCD_dsply, bcd_out => mux4x1_bcd_out);

u7: entity mux_4_3x1 port map (bcd0 => dig0_reg_q, bcd1 => dig1_qdcba, bcd2 => dig2_qdcba, sel => sel_BCD_cmpr,
bcd_out => mux3x1_bcd_out);

u8: entity reg_4bit port map (clk => clk, d => dig0_qdcba, en_bar => ld_BCD0_bar, q => dig0_reg_q);

u9: entity comparator_4bit port map (p => dig0_qdcba, q => mux3x1_bcd_out, equal => equal);

u10: entity control_fsm port map (clk => clk, rst_bar => rst_bar, start_bar => start_bar, ose_cten_bar => ose_cten_bar,
ose_dir_chngd => ose_dir_chngd, ose_up_bar => ose_up_bar, ld_BCD0_bar => ld_BCD0_bar,
sel_BCD_dsply => sel_BCD_dsply, sel_BCD_cmpr => sel_BCD_cmpr, fire => fire, digit_drive_bar => digit_drive_bar,
b => b, com_equal => equal, delay_timed_out => timed_out, no_of_bcds_eq => no_of_bcds_eq, dig0_cten_bar => en_dig0_bar,
dig12_cten_bar => free_run_bar, dig0_clear_bar => dig0_clear_bar, gd_cntr => gd_cntr,
en_gd_cntr_bar => en_gd_cntr_bar, passed_bar => passed_bar, failed_bar => failed_bar);

u11: entity delay port map (clk => clk, rst_bar => rst_bar, fire => fire, delayed_out => timed_out);

u12: entity result port map (clk => clk, gd_cntr => gd_cntr, en_gd_cntr_bar => en_gd_cntr_bar,
no_of_bcds_eq => no_of_bcds_eq);

end top_level;

Final Circuit (Lab - 12)

Circuit Description

Videos (.3gp format can be played by VLC player)

Passed

Failed